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1/18 december 2004 m36l0r7050t0 M36L0R7050B0 128 mbit (multiple bank, multi-level, burst) flash memory 32 mbit (2m x16) psram, 1.8v supply multi-chip package features summary multi-chip package ? 1 die of 128 mbit (8mb x16, multiple bank, multi-level, burst) flash memory ? 1 die of 32 mbit (2mb x16) asynchronous pseudo sram supply voltage ?v ddf = v ddp = v ddq = 1.7 to 1.95v ?v ppf = 9v for fast program (12v tolerant) electronic signature ? manufacturer code: 20h ? device code (top flash configuration) m36l0r7050t0: 88c4h ? device code (bottom flash configuration) M36L0R7050B0: 88c5h package ? compliant with lead-free soldering processes ? lead-free versions flash memory synchronous / asynchronous read ? synchronous burst read mode: 54mhz ? asynchronous page read mode ? random access: 85ns synchronous burst read suspend programming time ? 10s typical word program time using buffer program memory organization ? multiple bank memory array: 8 mbit banks ? parameter blocks (top or bottom location) dual operations ? program/erase in one bank while read in others ? no delay between read and write operations security ? 64 bit unique device number ? 2112 bit user programmable otp cells figure 1. package block locking ? all blocks locked at power-up ? any combination of blocks can be locked with zero latency ?wp f for block lock-down ? absolute write protection with v ppf = v ss common flash interface (cfi) 100,000 program/erase cycles per block psram access time: 85ns low standby current: 100a deep power-down current: 10a byte control: ub p /lb p programmable partial array 8 word page access capability: 25ns partial power-down modes ? deep power-down ? 4 mbit partial power-down ? 8 mbit partial power-down ? 16 mbit partial power-down tfbga88 (zaq) 8 x 10mm fbga
m36l0r7050t0, M36L0R7050B0 2/18 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 psram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 address inputs (a0-a22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 data input/output (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash chip enable (e f ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash output enable (g f ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash write enable (w f ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash write protect (wp f ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash reset (rp f ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash latch enable (l f ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash clock (k f ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 flash wait (wait f ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 psram chip enable (e1 p ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 psram chip enable (e2 p ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 psram output enable (g p ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 psram write enable (w p ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 psram upper byte enable (ub p ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 psram lower byte enable (lb p ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ddf supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ddp supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ddq supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ppf program supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ss ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 flash memory device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 psram device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. power-down configuration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3/18 m36l0r7050t0, M36L0R7050B0 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. ac measurement load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. flash memory dc characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. flash memory dc characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. psram dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch, bottom view outline15 table 10. stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch, package data. . . . . 15 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
m36l0r7050t0, M36L0R7050B0 4/18 summary description the m36l0r7050t0 and M36L0R7050B0 com- bine two memory devices in a multi-chip package: a 128-mbit, multiple bank flash memory, the m30l0r7000t0 or m30l0r7000b0, and a 32- mbit pseudosram, the m69ar048b. recom- mended operating conditions do not allow more than one memory to be active at the same time. the memory is offered in a stacked tfbga88 (8x10mm, 8x10 ball array, 0.8mm pitch) package. in addition to the standard version, the packages are also available in lead-free version, in compli- ance with jedec std j-std-020b, the st eco- pack 7191395 specification, and the rohs (restriction of hazardous substances) directive. all packages are compliant with lead-free solder- ing processes. the memory is supplied with all the bits erased (set to ?1?). figure 2. logic diagram table 1. signal names note: 1. a22-a21 are not connected to the psram component. ai08731 23 a0-a22 dq0-dq15 m36l0r7050t0 M36L0R7050B0 g f 16 w f rp f wp f e1 p g p w p ub p lb p v ss v ddf v ppf v ddp wait f l f k f v ddq e f e2 p a0-a22 (1) address inputs dq0-dq15 common data input/output v ddf power supply for flash memory v ddq flash memory power supply for i/o buffers v ppf flash optional supply voltage for fast program and erase v ss ground v ddp psram power supply nc not connected internally du do not use as internally connected flash memory l f latch enable input e f chip enable input g f output enable input w f write enable input rp f reset input wp f write protect input k f burst clock wait f wait data in burst mode psram e1 p chip enable input g p output enable input w p write enable input e2 p power-down input ub p upper byte enable input lb p lower byte enable input
5/18 m36l0r7050t0, M36L0R7050B0 figure 3. tfbga connections (top view through package) 8 7 6 5 4 3 2 1 c b a21 k f a4 a11 d e f du du w f v ss a19 a18 a22 a5 a12 v ss nc lb p a9 a3 a13 v ppf nc a17 a10 a20 a2 a15 l f wp f nc a7 a14 a8 a1 a16 rp f ub p a6 wait f dq13 a0 dq5 dq10 dq2 dq8 dq7 dq14 g p dq12 dq3 dq1 dq0 dq15 dq6 dq4 dq11 dq9 g f v ddq e f e2 p v ddp v ss v ss v ss v ss v ss v ddf v ddq v ss du du du du du du a g h j k ai08732 l m v ddf nc w p e p nc nc du du nc nc nc nc v ddq
m36l0r7050t0, M36L0R7050B0 6/18 signal descriptions see figure 2., logic diagram and table 1., signal names , for a brief overview of the signals connect- ed to this device. address inputs (a0-a22). addresses a0-a20 are common inputs for the flash memory and the psram components. the other lines (a21-a22) are inputs for the flash memory components only. the address inputs select the cells in the memory array to access during bus read operations. dur- ing bus write operations they control the com- mands sent to the command interface of the flash memory program/erase controller or they select the cells to access in the psram. the flash memory component is accessed through the chip enable signal (e f ) and through the write enable (w f ) signal, while the psram is accessed through two chip enable signals (e1 p and e2 p ) and the write enable signal (w p ). data input/output (dq0-dq15). in the flash memory the data i/o outputs the data stored at the selected address during a bus read operation or inputs a command or the data to be programmed during a write bus operation. in the psram the lower byte data inputs/out- puts, dq0-dq7, carry the data to or from the lower part of the selected address during a write or read operation, when lower byte enable (lb p ) is driven low. the upper byte data inputs/outputs, dq8-dq15, carry the data to or from the upper part of the se- lected address during a write or read operation, when upper byte enable (ub p ) is driven low. flash chip enable (e f ). the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip en- able is low, v il , and reset is high, v ih , the device is in active mode. when chip enable is at v ih the flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. flash output enable (g f ). the output enable input controls data output during flash memory bus read operations. flash write enable ( w f ). the write enable controls the bus write operation of the flash memories? command interface. the data and ad- dress inputs are latched on the rising edge of chip enable or write enable whichever occurs first. flash write protect (wp f ). write protect is an input that gives an additional hardware protection for each block. when write protect is low, v il , lock-down is enabled and the protection status of the locked-down blocks cannot be changed. when write protect is at high, v ih , lock-down is disabled and the locked-down blocks can be locked or unlocked. (see the lock status table in the m30l0r7000t0 datasheet). flash reset (rp f ). the reset input provides a hardware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 . refer to table 7., flash memory dc characteristics - cur- rents , for the value of i dd2 . after reset all blocks are in the locked state and the configuration reg- ister is reset. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, but a negative transition of chip enable or latch enable is re- quired to ensure valid data outputs. the reset pin can be interfaced with 3v logic with- out any additional circuitry. it can be tied to v rph (refer to table 8., flash memory dc characteris- tics - voltages ). flash latch enable (l f ). latch enable latches the address bits on its rising edge. the address latch is transparent when latch enable is low, v il , and it is inhibited when latch enable is high, v ih . latch enable can be kept low (also at board level) when the latch enable function is not required or supported. flash clock (k f ). the clock input synchronizes the flash memory to the microcontroller during synchronous read operations; the address is latched on a clock edge (rising or falling, accord- ing to the configuration settings) when latch en- able is at v il . clock is don't care during asynchronous read and in write operations. flash wait (wait f ). wait is a flash output sig- nal used during synchronous read to indicate whether the data on the output bus are valid. this output is high impedance when flash chip enable is at v ih or flash reset is at v il . it can be config- ured to be active during the wait cycle or one clock cycle in advance. the wait f signal is not gated by output enable. psram chip enable (e1 p ). when asserted (low), the chip enable, e1 p , activates the memo- ry state machine, address buffers and decoders, allowing read and write operations to be per- formed. when de-asserted (high), all other pins are ignored, and the device is put, automatically, in low-power standby mode. it is not allowed to set e f at v il, e1 p at v il and e2 p at v ih at the same time. psram chip enable (e2 p ). the chip enable, e2 p , puts the device in power-down mode (deep power-down or a partial power-down mode) when it is driven low. deep power-down mode is the lowest power mode.
7/18 m36l0r7050t0, M36L0R7050B0 it is not allowed to set e f at v il, e1 p at v il and e2 p at v ih at the same time. psram output enable (g p ). the output en- able, g p , provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common i/o data bus. psram write enable (w p ). the write enable, w p , controls the bus write operation of the device. psram upper byte enable (ub p ). the upper byte enable, ub p , gates the data on the upper byte data inputs/outputs (dq8-dq15) to or from the upper part of the selected address during a write or read operation. psram lower byte enable (lb p ). the lower byte enable, lb p , gates the data on the lower byte data inputs/outputs (dq0-dq7) to or from the lower part of the selected address during a write or read operation. v ddf supply voltage. v ddf provides the power supply to the internal cores of the flash memory component. it is the main power supply for all flash operations (read, program and erase). v ddp supply voltage. the v ddp supply volt- age supplies the power for all psram operations (read, write, etc.) and for driving the refresh logic, even when the device is not being accessed. v ddq supply voltage. v ddq provides the power supply for the flash memory i/o pins. this allows all outputs to be powered independently of the flash memory core power supply, v ddf . v ppf program supply voltage. v ppf is both a flash control input and a flash power supply pin. the two functions are selected by the voltage range applied to the pin. if v ppf is kept in a low voltage range (0v to v ddq ) v ppf is seen as a control input. in this case a volt- age lower than v pplkf gives an absolute protec- tion against program or erase, while v ppf > v pp1f enables these functions (see tables 7 and 8 , dc characteristics for the relevant values). v ppf is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v ppf is in the range of v pphf it acts as a power supply pin. in this condition v ppf must be stable until the program/erase algorithm is completed. v ss ground. v ss is the common ground refer- ence for all voltage measurements in the flash (core and i/o buffers) and psram chips. note: each flash memory device in a system should have their supply voltage (v ddf ) and the program supply voltage v ppf decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, inherently low inductance ca- pacitors should be as close as possible to the package). see figure 6., ac measurement load circuit . the pcb track widths should be sufficient to carry the required v ppf program and erase currents.
m36l0r7050t0, M36L0R7050B0 8/18 functional description the psram and flash memory components have separate power supplies but share the same grounds. they are distinguished by three chip en- able inputs: e f for the flash memory and e1 p and e2 p for the psram. recommended operating conditions do not allow more than one device to be active at a time. the most common example is simultaneous read oper- ations in the flash memory and the psram which would result in a data bus contention. therefore it is recommended to put the other device in the high impedance state when reading the selected de- vice. figure 4. functional block diagram ai08733 rp f wp f e1 p e2 p g p w p dq0-dq15 v ddf v ppf a21-a22 32 mbit psram g f w f ub p lb p wait f k f l f v ss 128 mbit flash memory v ddp e f a0-a20 v ddq
9/18 m36l0r7050t0, M36L0R7050B0 table 2. main operating modes note: 1. x = don't care. 2. l f can be tied to v ih if the valid address has been previously latched. 3. depends on g f . 4. wait signal polarity is configured using the set configurat ion register command. see the m30l0r7000t0 datasheet for details. operation e f g f w f l f rp f wait f (4) e1 p e2 p g p w p lb p ub p dq15-dq0 flash read v il v il v ih v il (2 ) v ih psram must be disabled flash data out flash write v il v ih v il v il (2 ) v ih flash data in flash address latch v il x v ih v il v ih flash data out or hi-z (3) flash output disable v il v ih v ih x v ih any psram mode is allowed hi-z flash standby v ih xx x v ih hi-z hi-z flash reset x x x x v il hi-z hi-z psram read flash memory must be disabled v il v ih v il v ih v ih v il upper byte data out v il v ih v il v ih v il v ih lower byte data out v il v ih v il v ih v il v il word read psram write v il v ih v ih v il v ih v il upper byte data in v il v ih v ih v il v il v ih lower byte data in v il v ih v ih v il v il v il word write output disable any flash mode is allowed v il v ih v il v ih v ih v ih hi-z v il v ih v ih v il v ih v ih psram standby (deselected) v ih v ih xxxx hi-z psram power- down x v il xxxx hi-z
m36l0r7050t0, M36L0R7050B0 10/18 flash memory device the m36l0r7050t0 and M36L0R7050B0 contain a 128 mbit flash memory. for detailed information on how to use the devices, see the m30l0r7000(t/b)0 datasheet which is available from the internet site http://www.st.com or from your local stmicroelectronics distributor. psram device the m36l0r7050t0 and M36L0R7050B0 contain a 32 mbit psram. this device can be placed in a number of sleep and partial sleep modes (see ta- ble 3. ). for detailed information on how to use the device, see the m69ar048b datasheet which is available from the internet site http://www.st.com or from your local stmicroelectronics distributor. table 3. power-down configuration data mode power-down configuration data dq15?dq9 dq8-dq2 dq1 dq0 deep power-down (default)0011 4mb partial power-down0010 8mb partial power-down0001 16mb partial power-down0000
11/18 m36l0r7050t0, M36L0R7050B0 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 4. absolute maximum ratings note: 1. compliant with the jedec std j-std-020b (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. symbol parameter value unit min max t a ambient operating temperature ?25 85 c t bias temperature under bias ?25 85 c t stg storage temperature ?55 125 c t lead lead temperature during soldering (1) c v io input or output voltage ?0.5 3.6 v v ddf , v ddq , v ddp core and input/output supply voltages ?0.2 2.5 v v ppf flash program voltage ?0.2 14 v i o output short circuit current 100 ma t vppfh time for v ppf at v ppfh 100 hours
m36l0r7050t0, M36L0R7050B0 12/18 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 5., operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 5. operating and ac measurement conditions figure 5. ac measurement i/o waveform note: v ddq = v ddp . figure 6. ac measurement load circuit table 6. device capacitance note: sampled only, not 100% tested. parameter flash memory psram unit min max min max v ddf supply voltage 1.7 1.95 ? ? v v ddp supply voltage ??1.71.95v v ddq supply voltage 1.7 1.95 ? ? v v ppf supply voltage (factory environment) 8.5 12.6 ? ? v v ppf supply voltage (application environment) ?0.4 v ddq +0.4 ??v ambient operating temperature ?25 85 ?30 85 c load capacitance (c l ) 30 50 pf output circuit resistors (r 1 , r 2 ) 16.7 16.7 k ? input rise and fall times 5 5 ns input pulse voltages 0 to v ddq 0 to v ddq v input and output timing ref. voltages v ddq /2 v ddq /2 v ai06161 v ddq 0v v ddq /2 ai08364b v ddq c l c l includes jig capacitance r 1 device under test 0.1f v ddq r 2 0.1f v ddf symbol parameter test condition min max unit c in input capacitance v in = 0v 12 pf c out output capacitance v out = 0v 15 pf
13/18 m36l0r7050t0, M36L0R7050B0 table 7. flash memory dc characteristics - currents note: 1. sampled only, not 100% tested. 2. v ddf dual operation current is the sum of read and program or erase currents. symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 1 a i dd1 supply current asynchronous read (f=6mhz) e f = v il , g f = v ih 10 15 ma supply current synchronous read (f=40mhz) 4 word 7 16 ma 8 word 10 18 ma 16 word 13 20 ma continuous 18 25 ma supply current synchronous read (f=54mhz) 4 word 16 18 ma 8 word 18 20 ma 16 word 21 25 ma continuous 22 27 ma i dd2 supply current (reset) rp f = v ss 0.2v 25 70 a i dd3 supply current (standby) e f = v ddf 0.2v 25 70 a i dd4 supply current (automatic standby) e f = v il , g f = v ih 25 70 a i dd5 (1) supply current (program) v ppf = v pph 815ma v ppf = v ddf 10 20 ma supply current (erase) v ppf = v pph 815ma v ppf = v ddf 10 20 ma i dd6 (1,2) supply current (dual operations) program/erase in one bank, asynchronous read in another bank 20 35 ma program/erase in one bank, synchronous read in another bank 32 47 ma i dd7 (1) supply current program/ erase suspended (standby) e f = v ddf 0.2v 25 70 a i pp1 (1) v ppf supply current (program) v ppf = v pph 25ma v ppf = v ddf 0.2 5 a v ppf supply current (erase) v ppf = v pph 25ma v ppf = v ddf 0.2 5 a i pp2 v ppf supply current (read) v ppf v ddf 0.2 5 a i pp3 (1) v ppf supply current (standby) v ppf v ddf 0.2 5 a
m36l0r7050t0, M36L0R7050B0 14/18 table 8. flash memory dc characteristics - voltages table 9. psram dc characteristics note: 1. maximum dc voltage on input and i/o pins is v ddp +0.2v. during voltage transitions, input may positive overshoot to v ddp + 1.0v for a period of up to 5ns. 2. minimum dc voltage on input or i/o pins is ?0.3v. during voltage transitions, input may positive overshoot to v ssp + 1.0v for a period of up to 5ns. symbol parameter test condition min typ max unit v il input low voltage ?0.5 0.4 v v ih input high voltage v ddq ?0.4 v ddq + 0.4 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage i oh = ?100a v ddq ?0.1 v v pp1 v ppf program voltage-logic program, erase 1.1 1.8 3.3 v v pph v ppf program voltage factory program, erase 8.5 9.0 12.6 v v pplk program or erase lockout 0.4 v v lko v ddf lock voltage 1v v rph rp f pin extended high voltage 3.3 v symbol parameter test condition min max unit i cc1 v ddp active current v ddp = 1.95v, v in = v ih or v il , e1 p = v il and e2 p = v ih , i out = 0ma t rc / t wc = minimum 25 ma i cc2 t rc / t wc = 1 s 3ma i cc3 v ddp page read current v ddp = 1.95v, v in = v ih or v il , e1 p = v il and e2 p = v ih , i out = 0ma, t prc = min. 10 ma i ccpd v ddp power-down current v ddp = 1.95v, v in = v ih or v il , e2 p 0.2v deep power- down 10 a i ccp4 4mb partial (3) 40 a i ccp8 8mb partial (3) 50 a i ccp16 16mb partial (3) 65 a i li input leakage current 0v v in v ddp ?1 1 a i lo output leakage current 0v v out v ddp ?1 1 a i sb standby supply current cmos v ddp = 1.95v, v in 0.2v or v in v ddp ?0.2v, e1 p = e2 p v ddp ?0.2v 100 a v ih (1) input high voltage 0.8v ddp v ddp + 0.2 v v il (2) input low voltage ?0.3 0.2v ddp v v oh output high voltage v ddp = 1.65v, i oh = ?0.5ma 1.4 v v ol output low voltage i ol = 1ma 0.4 v
15/18 m36l0r7050t0, M36L0R7050B0 package mechanical figure 7. stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch, bottom view outline note: drawing is not to scale. table 10. stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch, package data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.200 0.0079 a2 0.850 0.0335 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 d 8.000 7.900 8.100 0.3150 0.3110 0.3189 d1 5.600 0.2205 ddd 0.100 0.0039 e 10.000 9.900 10.100 0.3937 0.3898 0.3976 e1 7.200 0.2835 e2 8.800 0.3465 e 0.800 ? ? 0.0315 ? ? fd 1.200 0.0472 fe 1.400 0.0551 fe1 0.600 0.0236 sd 0.400 0.0157 se 0.400 0.0157 a2 a1 a bga-z42 ddd d e e b se fd e2 d1 sd ball "a1" e1 fe fe1
m36l0r7050t0, M36L0R7050B0 16/18 part numbering table 11. ordering information scheme devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available op- tions (speed, package, etc.) or for further information on any aspect of this device, please contact the st- microelectronics sales office nearest to you. example: m36 l 0 r 7 0 5 0 t 0 zaq t device type m36 = multi-chip package (multiple flash + ram) flash 1 architecture l = multilevel, multiple bank, burst mode flash 2 architecture 0 = no die operating voltage r = v ddf1 = v ddp = v ddq = 1.7 to 1.95v flash 1 density 7 = 128 mbit flash 2 density 0 = no die ram 1 density 5 = 32 mbit ram 0 density 0 = no die parameter blocks location t = top boot block flash b = bottom boot block flash product version 0 = 0.13m flash technology, 85ns speeds; 0.18m ram, 85ns speed package zaq = stacked tfbga88 8x10mm - 8x10 active ball array, 0.8mm pitch option blank = standard packing t = tape & reel packing e= lead-free and rohs package, standard packing f= lead-free and rohs package, tape and reel packing
17/18 m36l0r7050t0, M36L0R7050B0 revision history table 12. document revision history date version revision details 29-jul-2003 0.1 first issue 03-jun-2004 0.2 package specifications updated. psram component updated in accordance with m69ar048b datasheet. flash memory component updated in accordance with m30l0r7000(t/b)0 datasheet. document status changed from target specification to preliminary data. 04-dec-2004 1.0 tfbga88 package fully compliant with the st ecopack specification. document status promoted from preliminary data to full datasheet. flash memory and psram data updated to the version 1.0 of the m30l0r7000x0 datasheet and to the version 4.0 of the m69ar048b datasheet.
m36l0r7050t0, M36L0R7050B0 18/18 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. ecopack is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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